SD9268-125
16-bit, 125MHz, Dual Channel ADC
Overview & Features
The SD9268 is a dual-channel, 16-bit, analog-to-digital converter (ADC) supporting sampling rates up to 125MSps. The
device uses a multistage pipeline architecture to achieve high signal-to-noise ratio (SNR) and linearity, over wide input
signal bandwidth. The SD9268 can be set to operate using either CMOS or LVDS output interface. Programming for
configuration and control is accomplished using a 3-wire SPI-compatible serial bus. The digital output data can be
programmed to be delivered in offset binary, twos complement format, or gray code.
FEATURES
- SNR: 74.7dBFS at fIN = 70.2MHz and fS = 125MSps
- SFDR: 88.0dBc at fIN = 70.2MHz and fS = 125MSps
- -154.3dBFS/Hz input-noise at fIN = 70.2MHz and fS =
125MSps - 2.0Vp-p nominal input
- Typical power consumption: 425mW at 125MSps
- Integer 1-to-8 input clock divider (1000MHz maximum
input rate) - Sample rates of up to 125MSps
- 1.8V analog supply voltage
- LVDS (ANSI-644 levels) outputs
- Internal ADC voltage reference
- ADC clock duty cycle correction
- Serial port control
- Energy saving power-down modes
Specification
| Product Specifications | |||
|---|---|---|---|
| Resolution | 16-bit | Speed (Msps) | 125 |
| Number of Channels | 2 | SFDR (dBc)@70.2MHz | 88.23 |
| SNR (dBFS)@70.2MHz | 75.52 | ||
| Drop-in Replacement | Replacement Part # | Plural Price ($) | Replacement Part Price | Package |
|---|---|---|---|---|
| Yes | AD9268-125 | $125.21 | $178.87 | 64 pins (9x9 package) |
Stock, EVKs & Documentation
Last updated: March 18, 2026 7:52 pm