SD1150-105
16-bit, 105MHz, Dual Channel ADC
Overview & Features
The SD1150 is a dual-channel, 16-bit, analog-to-digital converter (ADC) supporting sampling rates up to 105MSps. The device uses a multistage pipeline architecture to achieve high signal-to-noise ratio (SNR) and linearity, over wide input signal bandwidth. The SD1150 can be set to operate using either CMOS or LVDS output interface. Programming for configuration and control is accomplished using a 3-wire SPI-compatible serial bus. The digital output data can be programmed to be delivered in offset binary, twos complement format, or gray code.
The device includes a DSP block that features decimation, digital down conversion (DDC), and IQ mismatch correction.
Features
* SNR: 74.7dBFS at fIN = 70.2MHz and fS = 105MSps
* SFDR: 87.0dBc at fIN = 70.2MHz and fS = 105MSps
* -153.7dBFS/Hz input-noise at fIN = 70.2MHz and fS = 105MSps
* 2.0V nominal input
* Typical power consumption: 380mW at 105MSps
* Integer 1-to-8 input clock divider (840MHz maximum input rate)
* Sample rates of up to 105MSps
* 1.8V analog supply voltage
* LVDS (ANSI-644 levels) outputs
* Internal ADC voltage reference
* ADC clock duty cycle correction
* Serial port control
* Decimation by 2, 4
* Digital Down-Convertion
* IQ Mismatch Correction
* Energy saving power-down modes
Specification
| Product Specifications | |||
|---|---|---|---|
| Resolution | 16-bit | Speed (Msps) | 105 |
| Number of Channels | 2 | SFDR (dBc)@70.2MHz | 87 |
| SNR (dBFS)@70.2MHz | 74.7 | ||
| Drop-in Replacement | Replacement Part # | Plural Price ($) | Replacement Part Price | Package |
|---|---|---|---|---|
| No | $ | $ | 64 pins (9x9 package) |