SD9251-65
14-bit, 65MHz, Dual Channel ADC
Specification
| Product Specifications | |||
|---|---|---|---|
| Resolution | 14-bit | Speed (Msps) | 65 |
| Number of Channels | 2 | SFDR (dBc)@70.2MHz | 86.39 |
| SNR (dBFS)@70.2MHz | 75.17 | ||
| Drop-in Replacement | Replacement Part # | Plural Price ($) | Replacement Part Price | Package |
|---|---|---|---|---|
| Yes | AD9251-65 | $32.40 | $46.29 | 64 pins (9x9 package) |
Overview & Features
The SD9251 is a dual-channel, 14-bit, analog-to-digital converter (ADC) supporting sampling rates up to 65MSps. The
device uses a multistage pipeline architecture to achieve high signal-to-noise ratio (SNR) and linearity, over wide input
signal bandwidth. The SD9251 uses a CMOS output interface to transfer the data out. Programming for configuration and
control is accomplished using a 3-wire SPI-compatible serial bus. The digital output data can be programmed to be
delivered in offset binary, twos complement format, or gray code.
FEATURES
- SNR: 74.8dBFS at fIN = 30.2MHz and fS = 65MSps
- SFDR: 91.0dBc at fIN = 30.2MHz and fS = 65MSps
- -151.5dBFS/Hz input-noise at fIN = 30.2MHz and fS =
65MSps - 2.0Vp-p nominal input
- Typical power consumption: 335mW at 65MSps
- Integer 1-to-8 input clock divider (520MHz maximum
input rate) - Sample rates of up to 65MSps
- 1.8V analog supply voltage
- Up to 3.3V digital I/O supply voltage
- Internal ADC voltage reference
- ADC clock duty cycle correction
- Serial port control
- Energy saving power-down modes
Stock, EVKs & Documentation
Last updated: January 15, 2026 1:00 am