The SD9608 uses a multistage pipeline architecture to provide 10-bit accuracy at 125MSps data rates and to guarantee no missing codes over the full operating temperature range.
The SD9608 features internal references and can operate without an external reference or external common-mode bias.
The device can be set to operate using either CMOS or LVDS output data formats. Programming for configuration and control is accomplished using a 3-wire SPI-compatible interface. The digital output data can be programmed to be delivered in offset binary, gray code, or twos complement format. Further, to decrease EMI, the output data can be scrambled. A data output clock (DCO+/DCO-) is provided for each ADC channel to ensure proper timing at the receiver.
• SNR: 61.5dBFS at fIN = 70.2MHz at fS = 125MSps
• SFDR: 76.0dBc at fIN = 70.2MHz at fS = 125MSps
• -143.6dBFS/Hz input-noise at fIN = 70.2MHz at fS =125MSps
• 2.0Vp-p nominal input
• Typical power consumption: 311mW at 125MSps
• Integer 1-to-8 input clock divider (1000MHz maximum input)
• Sample rates of up to 125MSps
• 1.8V analog supply voltage
• LVDS (ANSI-644 levels) outputs
• Internal ADC voltage reference
• ADC clock duty cycle correction
• Serial port control
• Energy saving power-down modes
