SD9650-65
16-bit, 65MHz, Dual Channel ADC
Specification
| Product Specifications | |||
|---|---|---|---|
| Resolution | 16-bit | Speed (Msps) | 65 |
| Number of Channels | 2 | SFDR (dBc)@70.2MHz | 86.51 |
| SNR (dBFS)@70.2MHz | 75.50 | ||
| Drop-in Replacement | Replacement Part # | Plural Price ($) | Replacement Part Price | Package |
|---|---|---|---|---|
| Yes | AD9650-65 | $88.55 | $126.50 | 64 pins (9x9 package) |
Overview & Features
The SD9650 is a dual-channel, 16-bit, analog-to-digital converter (ADC) supporting sampling rates up to 65MSps. The
device uses a multistage pipeline architecture to achieve high signal-to-noise ratio (SNR) and linearity, over wide input
signal bandwidth. The SD9650 can be set to operate using either CMOS or LVDS output interface. Programming for
configuration and control is accomplished using a 3-wire SPI-compatible serial bus. The digital output data can be
programmed to be delivered in offset binary, twos complement format, or gray code.
FEATURES
- SNR: 75.5dBFS at fIN = 30.2MHz and fS = 65MSps
- SFDR: 88.0dBc at fIN = 30.2MHz and fS = 65MSps
- -151.7dBFS/Hz input-noise at fIN = 30.2MHz and fS =
65MSps - 2.0Vp-p nominal input
- Typical power consumption: 340mW at 65MSps
- Integer 1-to-8 input clock divider (520MHz maximum
input rate) - Sample rates of up to 65MSps
- 1.8V analog supply voltage
- LVDS (ANSI-644 levels) outputs
- Internal ADC voltage reference
- ADC clock duty cycle correction
- Serial port control
- Energy saving power-down modes
Stock, EVKs & Documentation
Last updated: January 14, 2026 9:00 pm